This invention relates to flash memory arrays and in particular to the structures of flash memory arrays and methods of forming them.
All patents, patent applications, publications and other references cited in the present application are hereby incorporated by reference in their entirety.
There are many commercially successful nonvolatile memory products being used today, particularly in the form of small form factor cards, which use an array of flash EEPROM (Electrically Erasable and Programmable Read Only Memory) cells. Such cards may be interfaced with a host, for example, by removably inserting a card into a card slot in a host. Some of the commercially available cards are CompactFlash™ (CF) cards, MultiMedia cards (MMC), Secure Digital (SD) cards, Smart Media cards, personnel tags (P-Tag) and Memory Stick cards. Hosts include personal computers, notebook computers, personal digital assistants (PDAs), various data communication devices, digital cameras, cellular telephones, portable audio players, automobile sound systems, and similar types of equipment. In an alternative arrangement to the separate card and host described above, in some examples a memory system is permanently connected to a host providing an embedded memory that is dedicated to the host.
An example of a prior art memory system 100 is generally illustrated in the block diagram of FIG. 1. A large number of individually addressable memory cells are arranged in a regular array 110 of rows and columns, although other physical arrangements of cells are certainly possible. Bit lines, designated herein to extend along columns of the array 110, are electrically connected with a bit line decoder and driver circuit 130 through lines 150. Word lines, which are designated in this description to extend along rows of the array 110, are electrically connected through lines 170 to a word line decoder and driver circuit 190. Each of the decoders 130 and 190 receives memory cell addresses over a bus 160 from a memory controller 180. The decoder and driving circuits are also connected to the controller 180 over respective control and status signal lines 135 and 195.
The controller 180 is connectable through lines 140 to a host device (not shown). The host may be a personal computer, notebook computer, digital camera, audio player, various other hand held electronic devices, and the like. The memory system 100 of FIG. 1 will commonly be implemented in a card according to one of several existing physical and electrical standards, such as one from the PCMCIA, the CompactFlash.™. Association, the MMC.™. Association, and others. When in a card format, the lines 140 terminate in a connector on the card that interfaces with a complementary connector of the host device. The electrical interface of many cards follows the ATA standard, wherein the memory system appears to the host as if it was a magnetic disk drive. Other memory card interface standards also exist. In some systems, a memory card may not have a controller and the functions of the controller may be carried out by the host. As an alternative to the card format, a memory system of the type shown in FIG. 1 may be permanently embedded in the host device.
The decoder and driver circuits 130 and 190 generate appropriate voltages in their respective lines of the array 110, as addressed over the bus 160, according to control signals in respective control and status lines 135 and 195, to execute programming, reading and erasing functions. Any status signals, including voltage levels and other array parameters, are provided by the array 110 to the controller 180 over the same control and status lines 135 and 195. A plurality of sense amplifiers within the circuit 130 receive current or voltage levels that are indicative of the states of addressed memory cells within the array 110, and provides the controller 180 with information about those states over lines 145 during a read operation. A large number of sense amplifiers are usually used in order to be able to read the states of a large number of memory cells in parallel. During reading and program operations, one row of cells is typically addressed at a time through the circuits 190 for accessing a number of cells in the addressed row that are selected by the circuit 130. During an erase operation, all cells in each of many rows are typically addressed together as a block for simultaneous erasure.
Two general memory cell array architectures have found commercial application, NOR and NAND. In a typical NOR array, memory cells are connected between adjacent bit line source and drain diffusions that extend in a column direction with control gates connected to word lines extending along rows of cells. A memory cell includes at least one storage element positioned over at least a portion of the cell channel region between the source and drain. A programmed level of charge on the storage elements thus controls an operating characteristic of the cells, which can then be read by applying appropriate voltages to the addressed memory cells. Examples of such cells, their uses in memory systems and methods of manufacturing them are given in the following U.S. Pat. Nos. 5,070,032; 5,095,344; 5,313,421; 5,315,541; 5,343,063; 5,661,053 and 6,222,762. These patents, along with all other patents, patent applications and other publications referred to in this application are hereby incorporated by reference in their entirety for all purposes.
In a NAND array series strings of more than two memory cells, such as 16 or 32, are connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell. An example of a NAND architecture array and its operation as part of a memory system is found in the following U.S. Pat. Nos. 5,570,315; 5,774,397; 6,046,935 and 6,522,580. NAND memory devices have been found to be particularly suitable for mass storage applications such as those using removable memory cards.
FIG. 2A shows a portion of EEPROM cell array 110 of FIG. 1 having a NAND structure. Only a small portion of the repetitive structure is shown. NAND strings of memory cells are formed extending in the Y-direction. NAND strings include implanted source/drain regions that connect individual memory cells. A memory cell includes a floating gate overlying a channel region in the substrate. A series of word lines, WL0-WL3 extend across the memory array in the X-direction and overlie floating gates of memory cells of different strings. In addition, select gate lines (SSL, DSL) extend in the X-direction at either end of the NAND strings and overlie portions of the substrate to form select gates of select transistors that control the connection of NAND strings to memory control circuits. At one end of the NAND strings, a common source line (not shown) connects to each of the NAND strings. At the other end of the NAND strings, connections are made to bit lines (not shown). In a typical NAND memory array, NAND strings that share word lines and select lines form a block in the memory array that is erased as a unit. A typical string may include many memory cells, with 8, 16, 32 or more memory cells in a string being common Thus, a typical block may have 32 or more word lines extending across the NAND strings of the block. A block may have thousands of strings that are spaced apart in the X-direction. FIG. 2B shows a circuit diagram for the physical structure of FIG. 2A. FIG. 2B includes the common source line connecting the NAND strings at one end. NAND strings are shown extending between bit line connections and common source connections with select transistors controlling these connections.
FIG. 2C shows a cross sectional view of a NAND string of FIG. 2A (indicated by A-A in FIG. 2A). FIG. 2C more clearly shows the structure of individual memory cells having a floating gate (FG) formed from a first polysilicon layer (P1) and a control gate (CG) formed from a second polysilicon layer (P2). The control gate is formed by a portion of a word line that overlies a floating gate. In between a floating gate and a control gate is a dielectric layer 19. In addition, FIG. 2C shows implanted source/drain regions connecting adjacent cells in the NAND string. A gate dielectric layer is shown insulating floating gates from the substrate. Metal bit line contact and source contact are shown at either end of the NAND string. A source select transistor and a drain select transistor are shown having portions of both first polysilicon layer P1 and second polysilicon layer P2. For select transistors, these two layers are connected together so that no floating gate is formed. Alternatively, a single polysilicon layer may be used to form select gates.
The charge storage elements of current flash EEPROM arrays, as discussed in the foregoing referenced patents, are most commonly electrically conductive floating gates, typically formed from conductively doped polysilicon material. An alternate type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of the conductive floating gate to store charge in a non-volatile manner. A triple layer dielectric formed of silicon dioxide, silicon nitride and silicon oxide (ONO) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region, and erased by injecting hot holes into the nitride. Several specific cell structures and arrays employing dielectric storage elements and are described in U.S. Pat. No. 6,925,007. Thus, while examples given in the present application may refer to floating gates, other charge storage structures may also be used. The present application is not limited to a particular charge storage structure.
As in most integrated circuit applications, the pressure to shrink the silicon substrate area required to implement some integrated circuit function also exists with flash EEPROM systems. It is continually desired to increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types of packages, or to both increase capacity and decrease size. One way to increase the storage density of data is to store more than one bit of data per memory cell. This is accomplished by dividing a window of a floating gate charge level voltage range into more than two states. The use of four such states allows each cell to store two bits of data, eight states stores three bits of data per cell, and so on. A multiple state flash EEPROM structure and operation is described in U.S. Pat. Nos. 5,043,940 and 5,172,338, which patents are incorporated herein by this reference.
Increased data density can also be achieved by reducing the physical size of the memory cells and/or the overall array. Shrinking the size of integrated circuits is commonly performed for all types of circuits as processing techniques improve over time to permit implementing smaller feature sizes. But there are usually limits of how far a given circuit layout can be shrunk in this manner, since there is often at least one feature that is limited as to how much it can be shrunk. When this happens, designers will turn to a new or different layout or architecture of the circuit being implemented in order to reduce the amount of silicon area required to perform its functions. The shrinking of the above-described flash EEPROM integrated circuit systems can reach such limits.
One way to form small cells is to use a self-aligned Shallow Trench Isolation (STI) technique. This uses STI structures to isolate adjacent strings of floating gate cells such as those of NAND type memory arrays. According to this technique, a gate dielectric (tunnel dielectric) layer and floating gate polysilicon layer are formed first. Next, STI structures are formed by etching the gate dielectric and floating gate polysilicon layers and the underlying substrate to form trenches. These trenches are then filled with a suitable material (such as oxide) to form STI structures. The portions of the gate dielectric and floating gate polysilicon layers between STI structures are defined by the STI structures and are therefore considered to be self-aligned to the STI structures. Typically, the STI structures have a width that is equal to the minimum feature size that can be produced with the processing technology used. STI structures are also generally spaced apart by the minimum feature size. Thus, the portions of the gate dielectric and floating gate polysilicon layers between STI regions may also have a width that is equal to the minimum feature size. The strips of floating gate polysilicon are further formed into individual floating gates in later steps.
Another way to form small cells is to reduce the size of the features. However, lithographic processes used to establish the dimensions of devices are generally limited by some minimum feature size. Memory cells are generally designed to have dimensions that are equal to this minimum feature size (F). Thus, in FIG. 2A, the width of NAND strings and the separation between adjacent NAND strings is approximately F. Also, the width of the word lines and separation between adjacent word lines is approximately F. In one technique, sidewall spacers are grown that are narrower than F and used to form word lines that are narrower than F. An example of such a technique is described in U.S. Pat. No. 6,888,755.
While memory cells within a memory array may be scaled down in size using various techniques (including providing features that are smaller than the minimum feature size), peripheral circuits may not always be so easily scaled. Peripheral circuits include various circuits that are on the same substrate as a memory array and are used to manage the memory array. Examples of peripheral devices include word line decoder and driver circuits and bit line decoder and driver circuits. Peripheral circuits may have to withstand relatively large voltages so that they require relatively thick dielectric layers and relatively large device sizes. Because such peripheral circuits are not generally scaled down in size in proportion to the memory array, these peripheral circuits come to occupy an undesirably large area on a substrate.